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| - 1 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers act8942 advanced pmu for amlogi c aml8726-m3 processor features ? three step-down dc/dc converters ? four low-dropout linear regulators ? integrated activepath tm charger ? i 2 c tm serial interface ? advanced enable/disable sequencing controller ? minimal external components ? tiny 55mm tqfn55-40 package ? 0.75mm package height ? pb-free and rohs compliant general description the act8942 is a complete, cost effective, highly- efficient activepmu tm power management solution, optimized for the unique power, voltage- sequencing, and control requirements of the amlogic aml8726-m3 processor. it is ideal for a wide range of high performance portable handheld applications such as tablet or pad devices. this device integrates the activepath tm complete battery charging and management system with seven power supply channels. this device features three step-down dc/dc converters and four low-noise, low-dropout linear regulators, along with a complete battery charging solution featuring the advanced activepath tm system-power selection function. the three dc/dc converters utilize a high- efficiency, fixed-frequency (2mhz), current-mode pwm control architecture that requires a minimum number of external components. two dc/dcs are capable of supplying up to 1150ma of output current, while the third supports up to 1300ma. all four low-dropout linear regulators are high- performance, low-noise regul ators that supply up to 80ma, 320ma, 320ma, 320ma, respectively. the act8942 is available in a compact, pb-free and rohs-compliant tqfn55-40 package. typical application diagram rev 2, 15-nov-12
act8942 rev 2, 15-nov-12 - 2 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers table of contents general info rmation ........................................................................................................... .......................... p. 01 functional block diagram ...................................................................................................... ...................... p. 03 ordering in formation .......................................................................................................... .......................... p. 04 pin config uration ............................................................................................................. ............................ p. 04 pin descrip tions .............................................................................................................. ............................. p. 05 absolute maxi mum ratings ...................................................................................................... ................... p. 07 i 2 c interface electrical characteristics ........................................................................................ ................ p. 08 global regist er map ........................................................................................................... ......................... p. 09 register and bit descriptions ................................................................................................. ..................... p. 10 system control electric al characteristics ..................................................................................... ............... p. 15 step-down dc/dc electric al characteristics .................................................................................... .......... p. 16 low-noise ldo electric al characteristics ...................................................................................... ............. p. 17 activepath tm charger electrical characteristics .......................................................................................... p. 18 typical performance characteristics ........................................................................................... ................ p. 20 system control information .................................................................................................... ...................... p. 26 interfacing with the amlogic am l8726-m3 ...................................................................................... p. 26 control si gnals ............................................................................................................... .................. p. 27 push-button control ........................................................................................................... .............. p. 28 control s equences ............................................................................................................. .............. p. 28 functional de scription ........................................................................................................ ......................... p. 31 i 2 c interf ace ................................................................................................................... .................. p. 31 voltage monitor and interrupt ........................................................................................................... p. 31 thermal s hutdown .............................................................................................................. ............. p. 32 step-down dc/d c regulators .................................................................................................... ................ p. 33 general description .......................................................................................................................... p. 3 3 100% duty cycl e operat ion ..................................................................................................... ........ p. 33 synchronous re ctification ..................................................................................................... ........... p. 33 soft-start .................................................................................................................... ...................... p. 33 compensation .................................................................................................................. ................ p. 33 configuration options ....................................................................................................................... p. 33 ok[ ] and output f ault interrupt .............................................................................................. ......... p. 34 pcb layout cons iderations ..................................................................................................... ........ p. 34 low-noise, low-dropout linear regulators ................................................................................................ p. 35 general description .......................................................................................................................... p. 3 5 output curr ent limit .......................................................................................................... ............... p. 35 compensation .................................................................................................................. ................ p. 35 configuration options ....................................................................................................................... p. 35 ok[ ] and output f ault interrupt .............................................................................................. ......... p. 35 pcb layout cons iderations ..................................................................................................... ........ p. 35 activepath tm charger ...................................................................................................................... ............ p. 37 general description .......................................................................................................................... p. 3 7 activepath architecture ................................................................................................................. ... p. 37 system configuratio n optimization ............................................................................................. ..... p. 37 input prot ection .............................................................................................................. .................. p. 37 battery m anagement ............................................................................................................ ............ p. 37 charge current programming .................................................................................................... ...... p. 38 charger input interr upts ...................................................................................................... ............. p. 38 charge-control st ate machine .................................................................................................. ....... p. 40 state machine interrupts ...................................................................................................... ............ p. 40 thermal regu lation ............................................................................................................ .............. p. 41 charge safety timers .......................................................................................................... ............ p. 41 charger timer interrupts ...................................................................................................... ............ p. 41 charge status indicator........................................................................................................ ............ p. 41 reverse-current protection .................................................................................................... ......... p. 41 battery temperatur e monitoring ................................................................................................ ...... p. 41 battery temperat ure interrupts ................................................................................................ ........ p. 42 tqfn55-40 package out line and dime nsions ...................................................................................... ..... p. 43 act8942 rev 2, 15-nov-12 - 3 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers reg6 ldo reg7 ldo charge control chgin bat current sense voltage sense 4.35v to 6v ac adaptor usb li + battery body switch sda activepath control system supply vsys body switch 2.85v pre- condition 110c thermal regulation vp2 gp12 sw2 out2 out2 vp1 gp12 sw1 out1 out1 to vsys (optional) th out7 out6 reg5 ldo out5 out7 out6 out5 system control nirq reg4 ldo out4 out4 inl refbp reference acin iset vp3 gp3 sw3 out3 out3 + chglev ga ep nstat charge status vsys to vsys to vsys to vsys npbstat pwrhld pwren scl nrsto vsel nlbo 1.2v - + lbi out4 bat 102a out4 out4 out4 npbin push button vsys functional block diagram act8942 act8942 rev 2, 15-nov-12 - 4 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers lbi nlbo out3 vp3 sw3 gp3 npbstat nirq nrsto pwren vsys vsys chgin out2 vp2 sw2 gp12 sw1 vp1 nc pin configuration top view thin - qfn (tqfn55-40) ordering information part number v out1 /v stby1 v out2 /v stby2 v out3 /v stby3 v out4 v out5 v out6 v out7 package pins temperature range ACT8942QJ233-T 1.25v/1.25v 1.55v/1.55v 3.0v/3.0v 3.0v 3.0v 2.5v 3.3v tqfn55-40 40 -40c to +85c act8942qj133-t 1.25v/1.25v 1.55v/1.55v 3.0v/3.0v 3.0v 3.0v 2.5v 3.3v tqfn55-40 40 -40c to +85c : all active-semi components are rohs compliant and with pb-free plating otherwise specified. : standard product options are listed in this table. contact factory for custom options. minimum order quantity is 12,000 units . : to select v stbyx as the output regulation voltage for regx, drive vsel to logic high. v stbyx can be set by software via i 2 c interface. refer to appropriate sections of this datasheet for v stbyx setting. active aa33 date code act8942 rev 2, 15-nov-12 - 5 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers pin descriptions pin name description 1 refbp reference bypass. connect a 0.047 f ceramic capacitor from refbp to ga. this pin is discharged to ga in shutdown. 2 out1 output feedback sense for reg1. 3 ga analog ground. connect ga directly to a quiet ground node. connect ga, gp12 and gp3 together at a single point as close to the ic as possible. 4 out4 reg4 output. capable of delivering up to 80ma of output current. connect a 1.5f ceramic capacitor from out4 to ga. the output is discharged to ga with 1.5k ? resistor when disabled. 5 out5 reg5 output. capable of delivering up to 320m a of output current. connect a 3.3f ceramic capacitor from out5 to ga. the output is discharged to ga with 1.5k ? resistor when disabled. 6 inl power input for reg4, reg5, reg6, and reg7. bypass to ga with a high quality ceramic capacitor placed as close to the ic as possible. 7 out7 reg7 output. capable of delivering up to 320m a of output current. connect a 3.3f ceramic capacitor from out7 to ga. the output is discharged to ga with 1.5k ? resistor when disabled. 8 out6 reg6 output. capable of delivering up to 320m a of output current. connect a 3.3f ceramic capacitor from out6 to ga. the output is discharged to ga with 1.5k ? resistor when disabled. 9 npbin master enable input. drive npbin to ga through a 50k ? resistor to enable the ic, drive npbin directly to ga to a ssert a manual reset condition. refer to the npbin multi-function input section for more information. npbin is inte rnally pulled up to vsys through a 35k ? resistor. 10 pwrhld power hold input. refer to the control sequences section for more information. 11 nrsto active low reset output. see the nrsto output section for more information. 12 nirq open-drain interrupt output. nirq is asserted any time an unmasked fault condition exists or a charger interrupt occurs. see the nirq output section for more information. 13 npbstat active-low open-drain push-button status ou tput. npbstat is asse rted low whenever the npbin is pushed, and is high-z otherwise. see the npbstat output section for more information. 14 gp3 power ground for reg3. connect ga, gp12, and gp3 together at a single point as close to the ic as possible. 15 sw3 switching node output for reg3. 16 vp3 power input for reg3. bypass to gp 3 with a high quality ceramic capacitor placed as close to the ic as possible. 17 out3 output feedback sense for reg3. 18 pwren power enable input. refer to the control sequences section for more information. 19 nlbo low battery indicator output. nlbo is asserted lo w whenever the voltage at lbi is lower than 1.2v, and is high-z otherwise. see the precision voltage detector section for more information. 20 lbi low battery input. the input voltage is compared to 1.2v and the output of this comparison drives nlbo. see the precision voltage detector section for more information. 21 acin ac input supply detection. see the charge current programming section for more information. 22 chglev charge current selection input. see the charge current programming section for more information. act8942 rev 2, 15-nov-12 - 6 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers pin descriptions cont?d pin name description 25 vsel step-down dc/dcs output voltage selection. drive to logic low to select default output voltage. drive to logic high to select secondary output voltage. see the output voltage programming section for more information. 26 scl clock input for i 2 c serial interface. 27 sda data input for i 2 c serial interface. data is read on the rising edge of scl. 28 nstat active-low open-drain charger status output. ns tat has a 8ma (typ) current limit, allowing it to directly drive an indicator led without additional external components. see the charge status indicator section for more information. 29, 30 bat battery charger outpu t. connect this pin directly to the battery anode (+ terminal) 31, 32 vsys system output pin. bypass to ga with a 10f or lar ger ceramic capacitor. 33 chgin power input for the battery char ger. bypass chgin to ga with a capacitor placed as close to the ic as possible. 34 out2 output feedback sense for reg2. 35 vp2 power input for reg2. bypass to gp12 with a high quality ceramic capacitor placed as close to the ic as possible. 36 sw2 switching node output for reg2. 37 gp12 power ground for reg1 and reg2. connect ga, gp12 and gp3 together at a single point as close to the ic as possible. 38 sw1 switching node output for reg1. 39 vp1 power input for reg1. bypass to gp12 with a high quality ceramic capacitor placed as close to the ic as possible. 40 nc no connect. not internally connected. ep ep exposed pad. must be soldered to ground on pcb. 24 th temperature sensing input. connect to battery thermi stor. th is pulled up with a 102a (typ) current internally. see the battery temperature monitoring section for more information. 23 iset charge current set. program the charge current by connecting a resistor (r iset ) between iset and ga. see the charge current programming section for more information. act8942 rev 2, 15-nov-12 - 7 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers absolute maximum ratings parameter value unit vp1, vp2 to gp12 vp3 to gp3 -0.3 to + 6 v chgin to ga -0.3 to + 14 v sw1, out1 to gp12 -0.3 to (v vp1 + 0.3) v sw3, out3 to gp3 -0.3 to (v vp3 + 0.3) v npbin, acin, chglev, iset, lbi, pwrhl d, pwren, refbp, scl, sda, th, vsel to ga -0.3 to (vsys+ 0.3) v out4, out5, out6, out7 to ga -0.3 to (v inl + 0.3) v gp12, gp3 to ga -0.3 to + 0.3 v operating ambient temper ature -40 to 85 c maximum junction temperature 125 c maximum power dissipation tqfn55-40 (thermal resistance ja = 30 o c/w) 2.7 w storage temperature -65 to 150 c lead temperature (soldering, 10 sec) 300 c bat, vsys, inl to ga -0.3 to + 6 v sw2, out2 to gp12 -0.3 to (v vp2 + 0.3) v nirq, nlbo, npbstat, nrsto, nstat to ga -0.3 to + 6 v : do not exceed these limits to prevent damage to the device. exposure to absolute maximum rati ng conditions for long periods m ay affect device reliability. act8942 rev 2, 15-nov-12 - 8 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers figure 1: i 2 c compatible serial bus timing (v vsys = 3.6v, t a = 25c, unless otherwise specified.) i 2 c interface electrical characteristics sda scl t st t su t hd t sp t scl start condition stop condition parameter test conditions min typ max unit scl, sda input low v vsys = 3.1v to 5.5v, t a = -40oc to 85oc 0.35 v scl, sda input high v vsys = 3.1v to 5.5v, t a = -40oc to 85oc 1.55 v sda leakage current 1 a sda output low i ol = 5ma 0.35 v scl clock period, t scl 1.5 s sda data setup time, t su 100 ns sda data hold time, t hd 300 ns start setup time, t st for start condition 100 ns stop setup time, t sp for stop condition 100 ns scl leakage current 8 18 a act8942 rev 2, 15-nov-12 - 9 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers output address d7 d6 d5 d4 d3 d2 d1 d0 sys 0x00 name trst nsysmode nsyslevmsk nsysstat syslev[3] syslev[2] syslev[1] syslev[0] default 0 1 0 r 0 1 1 1 sys 0x01 name reserved reserved reserved reserved scratch scratch scratch scratch default 0 0 0 0 0 0 0 0 reg1 0x20 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default 0 0 0 1 1 0 0 1 reg1 0x21 name reserved reserved vset2[5] vset2[4] vset2[3] vset2[2] vset2[1] vset2[0] default 0 0 0 1 1 0 0 1 reg1 0x22 name on phase mode delay[2] delay[1] delay[0] nfltmsk ok default 0 0 0 0 0 1 0 r reg2 0x30 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default 0 0 0 1 1 1 1 1 reg2 0x31 name reserved reserved vset2[5] vset2[4] vset2[3] vset2[2] vset2[1] vset2[0] default 0 0 0 1 1 1 1 1 reg2 0x32 name on phase mode delay[2] delay[1] delay[0] nfltmsk ok default 0 0 0 0 0 1 0 r reg3 0x40 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default 0 0 1 1 0 1 1 0 reg3 0x41 name reserved reserved vset2[5] vset2[4] vset2[3] vset2[2] vset2[1] vset2[0] default 0 0 1 1 0 1 1 0 reg3 0x42 name on reserved mode delay[2] delay[1] delay[0] nfltmsk ok default 0 0 0 0 1 0 0 r reg4 0x50 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default 0 0 1 1 0 1 1 0 reg4 0x51 name on dis lowiq delay[2] delay[1] delay[0] nfltmsk ok default 0 1 0 0 0 0 0 r reg5 0x54 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default 0 0 1 1 0 1 1 0 reg5 0x55 name on dis lowiq delay[2] delay[1] delay[0] nfltmsk ok default 0 1 0 0 1 0 0 r reg6 0x60 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default 0 0 1 1 0 0 0 1 reg6 0x61 name on dis lowiq delay[2] delay[1] delay[0] nfltmsk ok default 0 1 0 0 1 0 0 r reg7 0x64 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default 0 0 1 1 1 0 0 1 reg7 0x65 name on dis lowiq delay[2] delay[1] delay[0] nfltmsk ok default 0 1 0 0 1 0 0 r apch 0x70 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 1 0 1 0 0 0 0 apch 0x71 name suschg reserved tottimo[1] tottimo[0] pretimo[1] pretimo[0] ovpset[1] ovpset[0] default 0 1 1 0 1 0 0 0 apch 0x78 name timrstat tempstat instat chgstat timrdat tempdat indat chgdat default 0 0 0 0 r r r r apch 0x79 name timrtot tempin incon chgeocin timrpre tempout indis chgeocout default 0 0 0 0 0 0 0 0 apch 0x7a name reserved reserved cstate[0] cstate[1] reserved reserved acinstat reserved default 0 0 r r r r r r bits global register map : default values of ACT8942QJ233-T. 2 : all bits are automatically cleared to default values when t he input power is removed or falls below the system uvlo. act8942 rev 2, 15-nov-12 - 10 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers register and bit descriptions table 1: global register map output address bit name access description sys 0x00 [7] trst r/w reset timer setting. defines the re set time-out th reshold. reset time-out is 65ms when value is 1, reset time-out is 260ms when value is 0. see nrsto output section for more information. sys 0x00 [6] nsysmode r/w syslev mode select. defines the response to the syslev voltage detector, 1: g enerate an interrupt when v vsys falls below the programmed syslev threshold, 0: automatic shutdown when v vsys falls below the prog rammed syslev threshold. sys 0x00 [5] nsyslevmsk r/w system voltage level interru pt mask. syslev interrupt is masked by default, set to 1 to unmask this interrupt. see the programmable system voltage monitor section for more information sys 0x00 [4] nsysstat r system voltage status. value is 1 when v vsys is lower than the syslev voltage threshold, value is 0 when v vsys is higher than the system voltage detection threshold. sys 0x00 [3:0] syslev r/w system voltage detect thres hold. defines the syslev voltage threshold. see the programmable system voltage monitor section for more information. sys 0x01 [7:4] - r reserved. sys 0x01 [3:0] scratch r/w scratchpad bits. non-functional bits, maybe be used by user to store system status information. volatile bits, which are cleared when system voltage falls below uvlo threshold. reg1 0x20 [7:6] - r reserved. reg1 0x20 [5:0] vset1 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information. reg1 0x21 [7:6] - r reserved. reg1 0x21 [5:0] vset2 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg1 0x22 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg1 0x22 [6] phase r/w regulator phase control. set bit to 1 for the regulator to operate 180 out of phase with the oscillator, clear bit to 0 for the regulator to operate in phase with the oscillator. reg1 0x22 [5] mode r/w regulator mode select. set bi t to 1 for fixed-frequency pwm under all load conditions, clear bit to 0 to transit to power-savings mode under light-load conditions. reg1 0x22 [4:2] delay r/w regulator turn-on delay control. see the reg1, reg2, reg3 turn-on delay section for more information. reg1 0x22 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg1 0x22 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault-interrupts, clear bit to 0 to disa ble fault-interrupts. act8942 rev 2, 15-nov-12 - 11 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers register and bit descriptions cont?d output address bit name access description reg2 0x30 [7:6] - r reserved. reg2 0x30 [5:0] vset1 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information. reg2 0x31 [7:6] - r reserved. reg2 0x31 [5:0] vset2 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg2 0x32 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg2 0x32 [6] phase r/w regulator phase control. set bi t to 1 for the regulator to operate 180 out of phase with the oscillator, clear bit to 0 for the regulator to operate in phase with the oscillator. reg2 0x32 [5] mode r/w regulator mode select. set bi t to 1 for fixed-frequency pwm under all load conditions, clear bit to 0 to transit to power- savings mode under light-load conditions. reg2 0x32 [4:2] delay r/w regulator turn-on delay control. see the reg1, reg2, reg3 turn-on delay section for more information. reg2 0x32 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault- interrupts, clear bit to 0 to disable fault-interrupts. reg2 0x32 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg3 0x40 [7:6] - r reserved. reg3 0x40 [5:0] vset1 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information. reg3 0x41 [7:6] - r reserved. reg3 0x41 [5:0] vset2 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg3 0x42 [7] on r/w regulator enable bit. se t bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg3 0x42 [6] - r reserved. reg3 0x42 [5] mode r/w regulator mode select. set bi t to 1 for fixed-frequency pwm under all load conditions, clear bit to 0 to transit to power- savings mode under light-load conditions. reg3 0x42 [4:2] delay r/w regulator turn-on delay control. see the reg1, reg2, reg3 turn-on delay section for more information. reg3 0x42 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault- interrupts, clear bit to 0 to disable fault-interrupts. reg3 0x42 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. act8942 rev 2, 15-nov-12 - 12 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers register and bit descriptions cont?d output address bit name access description reg4 0x50 [7:6] - r reserved. reg4 0x50 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg4 0x51 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg4 0x51 [6] dis r/w output discharge control. w hen activated, ldo output is discharged to ga through 1.5k ? resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg4 0x51 [5] lowiq r/w ldo low-iq mode control. set bit to 1 for low-power operating mode, clear bit to 0 for normal mode. reg4 0x51 [4:2] delay r/w regulator turn-on delay control. see the reg4, reg5, reg6, reg7 turn-on delay section for more information. reg4 0x51 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault- interrupts, clear bit to 0 to disable fault-interrupts. reg4 0x51 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg5 0x54 [7:6] - r reserved. reg5 0x54 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg5 0x55 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg5 0x55 [6] dis r/w output discharge control. w hen activated, ldo output is discharged to ga through 1.5k ? resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg5 0x55 [5] lowiq r/w ldo low-iq mode control. set bit to 1 for low-power operating mode, clear bit to 0 for normal mode. reg5 0x55 [4:2] delay r/w regulator turn-on delay control. see the reg4, reg5, reg6 , reg7 turn-on delay section for more information. reg5 0x55 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault- interrupts, clear bit to 0 to disable fault-interrupts. reg5 0x55 [0] ok r regulator power-ok status. value is 1 when output voltage exceeds the power-ok threshold, value is 0 otherwise. reg6 0x60 [7:6] - r reserved. reg6 0x60 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg6 0x61 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg6 0x61 [6] dis r/w output discharge control. w hen activated, ldo output is discharged to ga through 1.5k ? resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg6 0x61 [5] lowiq r/w ldo low-iq mode control. set bit to 1 for low-power operating mode, clear bit to 0 for normal mode. reg6 0x61 [4:2] delay r/w regulator turn-on delay control. see the reg4, reg5, reg6, reg7 turn-on delay section for more information. reg6 0x61 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault- interrupts, clear bit to 0 to disable fault-interrupts. act8942 rev 2, 15-nov-12 - 13 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers register and bit descriptions cont?d : valid only when chgin uvlo threshold act8942 rev 2, 15-nov-12 - 15 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers system control electr ical characteristics (v vsys = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit input voltage range 2.7 5.5 v uvlo threshold voltage v vsys rising 2.2 2.45 2.65 v uvlo hysteresis v vsys falling 200 mv supply current reg1, reg2, reg4 enabled. reg3, reg5, reg6 and reg7 disabled. 250 a all regulators enabled 420 shutdown supply current all regulators disabled 8 18 a oscillator frequency 1.8 2 2.2 mhz logic high input voltage 1 1.4 v logic low input voltage 0.4 v leakage current v nirq = v nrsto = 4.2v 1 a lbi threshold voltage vbat falling 1.03 1.2 1.31 v lbi hysteresis threshold vbat rising 200 mv low level output voltage 2 i sink = 5ma 0.35 v nrsto delay 260 ms thermal shutdown temperature temperature rising 160 c thermal shutdown hysteresis 20 c : pwrhld, pwren, vsel are logic inputs. 2 : nlbo, npbstat, nirq, nrsto are open drain outputs. 3 : typical value shown. actual value may vary from 227.9ms to 291.2ms. act8942 rev 2, 15-nov-12 - 16 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers step-down dc/dc electrical characteristics (v vp1 = v vp2 = v vp3 = 3.6v, t a = 25c, unless otherwise specified.) parameter conditions min typ max unit operating voltage range 2.7 5.5 v uvlo threshold input volt age rising 2.5 2.6 2.7 v uvlo hysteresis input voltage falling 100 mv quiescent supply current regulator enabled 65 90 a shutdown current v vp = 5.5v, regulator disabled 0 1 a output voltage accuracy v out 1.2v, i out = 10ma -1% v nom 1% v out < 1.2v, i out = 10ma -2% v nom 2% line regulation v vp = max (v nom 1 +1, 3.2v) to 5.5v 0.15 %/v load regulation i out = 10ma to imax 2 0.0017 %/ma power good threshold v out rising 93 %v nom power good hysteresis v out falling 2 %v nom oscillator frequency v out 20% of v nom 1.8 2 2.2 mhz v out = 0v 500 khz soft-start period 400 s minimum on-time 75 ns reg1 maximum output current 1.15 a current limit 1.5 1.8 2.1 a pmos on-resistance i sw1 = -100ma 0.16 ? nmos on-resistance i sw1 = 100ma 0.16 ? sw1 leakage current v vp1 = 5.5v, v sw1 = 0 or 5.5v 0 1 a reg2 maximum output current 1.15 a current limit 1.5 1.8 2.1 a pmos on-resistance i sw2 = -100ma 0.16 ? nmos on-resistance i sw2 = 100ma 0.16 ? sw2 leakage current v vp2 = 5.5v, v sw2 = 0 or 5.5v 0 1 a reg3 maximum output current 1.3 a current limit 1.7 2.1 2.5 a pmos on-resistance i sw3 = -100ma 0.16 ? nmos on-resistance i sw3 = 100ma 0.16 ? sw3 leakage current v vp3 = 5.5v, v sw3 = 0 or 5.5v 0 1 a v : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. 2 : imax maximum output current. act8942 rev 2, 15-nov-12 - 17 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers low-noise ldo electri cal characteristics (v inl = 3.6v, c out4 = 1.5f, c out5 = c out6 = c out7 = 3.3f, lowiq[ ] = [0], t a = 25c, unless otherwise specified.) : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. 2 : imax maximum output current. 3 : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage (for 3.1v output voltage or higher) : ldo current limit is defined as the output current at which th e output voltage drops to 95% of the respective regulation volt age. parameter test conditions min typ max unit operating voltage range 2.5 5.5 v output voltage accuracy v out 1.2v, t a = 25c, i out = 10ma -1% v nom 2% v v out < 1.2v, t a = 25c, i out = 10ma -2% v nom 4% line regulation v inl = max (v out + 0.5v, 3.6v) to 5.5v lowiq[ ] = [0] 0.05 v inl = max (v out + 0.5v, 3.6v) to 5.5v lowiq[ ] = [1] 0.5 load regulation i out = 1ma to imax 2 0.08 v/a power supply rejection ratio f = 1khz, i out = 20ma, v out =1.2v 75 db f = 10khz, i out = 20ma, v out =1.2v 65 supply current per output regulator enabled, low iq[ ] = [0] 37 60 a regulator enabled, low iq[ ] = [1] 31 52 regulator disabled 0 1 soft-start period v out = 2.9v 140 s power good threshold v out rising 89 % power good hysteresis v out falling 3 % output noise i out = 20ma, f = 10hz to 100khz, v out = 1.2v 50 v rms discharge resistance ldo disabled, dis[ ] = 1 1.5 k ? reg4 dropout voltage i out = 40ma, v out > 3.1v 90 180 mv maximum output current 80 ma current limit v out = 95% of regulation voltage 100 ma stable c out4 range 1.5 20 f reg5 dropout voltage i out = 160ma, v out > 3.1v 140 280 mv maximum output current 320 ma current limit v out = 95% of regulation voltage 400 ma stable c out5 range 3.3 20 f reg6 dropout voltage i out = 160ma, v out > 3.1v 90 180 mv maximum output current 320 ma current limit v out = 95% of regulation voltage 400 ma stable c out6 range 3.3 20 f reg7 dropout voltage i out = 160ma, v out > 3.1v 140 280 mv maximum output current 320 ma current limit v out = 95% of regulation voltage 400 ma stable c out7 range 3.3 20 f mv/v act8942 rev 2, 15-nov-12 - 18 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers activepath tm charger electrical characteristics (v chgin = 5.0v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit activepath chgin operating voltage range 4.35 6.0 v chgin uvlo threshold chgin voltage rising 3.1 3.5 3.9 v chgin uvlo hysteresis chgin voltage falling 0.5 v chgin ovp threshold chgin voltage rising 6.0 6.6 7.2 v chgin ovp hysteresis chgin voltage falling 0.4 v chgin supply current v chgin < v uvlo 35 70 a v chgin < v bat + 50mv, v chgin > v uvlo 100 200 a v chgin > v bat + 150mv, v chgin > v uvlo charger disabled, i vsys = 0ma 1.3 2.0 ma chgin to vsys on-resistance i vsys = 100ma 0.3 ? chgin to vsys current limit acin = vsys 1.5 2 a acin = ga, chglev = ga 80 90 100 ma acin = ga, chglev = vsys 400 450 500 vsys regulation vsys regulated voltage i vsys = 10ma 4.45 4.6 4.8 v nstat output nstat sink current v nstat = 2v 4 8 12 ma nstat leakage current v nstat = 4.2v 1 a acin and chglev inputs chglev logic high input voltage 1.4 v chglev logic low input voltage 0.4 v chglev leakage current v chglev = 4.2v 1 a acin voltage thresholds acin voltage rising 1.03 1.2 1.31 v acin hysteresis voltage acin voltage falling 200 mv acin leakage current v acin = 4.2v 1 a th input th pull-up current v chgin > v bat + 100mv, hysteresis = 50mv 91 102 110 a v th upper temperature voltage threshold (v thh ) hot detect ntc thermistor 2.44 2.51 2.58 v v th lower temperature voltage threshold (v thl ) cold detect ntc thermistor 0.47 0.50 0.53 v v th hysteresis upper and lower thresholds 30 mv act8942 rev 2, 15-nov-12 - 19 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers activepath tm charger electrical characteristics cont?d (v chgin = 5.0v, t a = 25c, unless otherwise specified.) : r iset (k ? ) = 2336 (1v/i chg (ma)) - 0.205 parameter test conditions min typ max unit charger bat reverse leakage current v chgin = 0v, v bat = 4.2v, i vsys = 0ma 8 a bat to vsys on-resistance 70 m ? iset pin voltage fast charge 1.2 v precondition 0.13 charge termination voltage v term t a = -20c to 70c 4.179 4.2 4.221 v t a = -40c to 85c 4.170 4.2 4.230 charge current v bat = 3.8v r iset = 6.8k acin = vsys, chglev = vsys -10% i chg 1 +10% ma acin = vsys, chglev = ga -10% i chg /5 +10% acin = ga, chglev = vsys 400 450 500 acin = ga, chglev = ga 80 90 100 precondition charge current v bat = 2.7v r iset = 6.8k acin = vsys, chglev = vsys 10% i chg ma acin = vsys, chglev = ga 10% i chg acin = ga, chglev = vsys 45 acin = ga, chglev = ga 45 precondition threshold voltage v bat voltage rising 2.75 2.85 3.0 v precondition threshold hysteresis v bat voltage falling 150 mv end-of-charge current threshold v bat = 4.15v acin = vsys, chglev = vsys 10% i chg acin = vsys, chglev = ga 10% i chg charge restart threshold v term - v bat , v bat falling 190 205 220 mv precondition safety timer pretimo[ ] = 10 80 min total safety timer tottimo[ ] = 10 5 hr thermal regulation threshold 100 c ma acin = ga, chglev = ga 45 acin = ga, chglev = vsys 45 act8942 rev 2, 15-nov-12 - 20 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers typical performanc e characteristics (v vsys = 3.6v, t a = 25c, unless otherwise specified.) temperature (c) -40 -20 0 20 40 60 80 100 120 act8942-001 v ref vs. temperature v ref (%) act8942-006 pwren sequence ch1: v pwrhld , 2v/div ch2: v out4 , 2v/div ch3: v out1 , 1v/div ch4: v out2 , 1v/div time: 2ms/div ch1 ch2 ch3 ch4 act8942-002 frequency vs. temperature frequency (%) temperature (c) -40 -20 0 20 40 60 80 85 typical v ref =1.2v typical oscillator frequency=2mhz 0.84 0.42 0 -0.42 -0.84 2.5 2 1.5 1 0.5 0 -0.5 -1 act8942-003 npbin startup sequence ch1 ch2 ch3 ch1: v npbin , 2v/div ch2: v out4 , 2v/div ch3: v out1 , 1v/div ch4: v out3 , 2v/div ch5: v out2 , 1v/div ch6: v out5 , 2v/div time: 2ms/div ch4 ch5 act8942-005 pwrhld startup sequence ch1 ch1: v pwren , 2v/div ch2: v out3 , 2v/div ch3: v out5 , 2v/div ch4: v out6 , 2v/div ch5: v out7 , 2v/div time: 2ms/div ch2 ch3 ch4 ch5 act8942-004 npbin startup sequence ch1 ch2 ch3 ch1: v npbin , 2v/div ch2: v out4 , 2v/div ch3: v out6 , 1v/div ch4: v out7 , 2v/div time: 2ms/div ch4 ch6 act8942 rev 2, 15-nov-12 - 21 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers act8942-007 push-button response (first power-up) (t a = 25c, unless otherwise specified.) act8942-009 reg1 efficiency vs. output current efficiency (%) output current (ma) 1 10 100 1000 act8942-010 reg2 efficiency vs. output current 100 80 60 40 20 0 efficiency (%) output current (ma) 1 10 100 1000 100 80 60 40 20 0 act8942-011 reg3 efficiency vs. output current 100 80 60 40 20 0 efficiency (%) output current (ma) 1 10 100 1000 typical performance ch aracteristics cont?d ch1 ch2 ch3 manual reset response ch1 ch2 ch3 act8942-008 ch1: v npbin , 2v/div ch2: v npbstat , 2v/div ch3: v nrsto , 2v/div time: 100ms/div npbin resistor = 50k ? ch1: v npbin , 2v/div ch2: v npbstat , 2v/div ch3:v nrsto , 2v/div time: 100ms/div npbin resistor = 0 ? v out = 1.8v v in = 3.6v v in = 4.2v v in = 5.0v v out = 3.3v v in = 3.6v v in = 4.2v v in = 5.0v v out = 1.2v v in = 4.2v v in = 3.6v v in = 5.0v act8942 rev 2, 15-nov-12 - 22 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers (t a = 25c, unless otherwise specified.) typical performance ch aracteristics cont?d act8942-013 reg1, 2, 3 mosfet resistance r dson (m ? ) input voltage (v) 3.0 3.5 4.0 4.5 5.0 5.5 300 250 200 150 100 50 0 350 i load = 100ma pmos nmos act8942-015 4% 2% 0% -2% -4% -6% error percent (%) error voltage percent vs. output current output current (ma) 0 50 100 150 200 250 300 350 400 reg5, reg6, reg7 v out > 1.2v v out 1.2v reg4, reg5, reg6, reg7 temperature (c) -40 -20 0 20 40 60 80 act8942-016 error voltage percent vs. temperature 4% 2% 0% -2% -4% error percent (%) v out > 1.2v v out 1.2v output current (ma) 0 10 20 30 40 50 60 70 80 90 100 act8942-017 dropout voltage vs. output current dropout voltage (mv) 250 200 150 100 50 0 reg4 v in = 3.3v temperature (c) -40 -20 0 20 40 60 80 100 120 act8942-012 error voltage percent vs. temperature error percent (%) 0.02 0.01 0 -0.01 -0.02 v out > 1.2v v out 1.2v reg1, reg2, reg3 i load = 10ma act8942-014 2% 1% 0 -1% -2% error percent (%) error voltage percent vs. output current output current (ma) 0 10 20 30 40 50 60 70 80 90 100 v out 1.2v v out > 1.2v reg4 act8942 rev 2, 15-nov-12 - 23 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers (t a = 25c, unless otherwise specified.) typical performance ch aracteristics cont?d output current (ma) 0 50 100 150 200 250 300 350 400 act8942-018 dropout voltage vs. output current dropout voltage (mv) 250 200 150 100 50 0 reg6 v in = 3.3v act8942-019 dropout voltage vs. output current dropout voltage (mv) 350 200 150 100 50 0 300 250 reg5, reg7 v in = 3.3v output current (ma) 0 50 100 150 200 250 300 350 400 esr ( ? ) act8942-020 region of stable c out esr vs. output current 1 0.1 0.01 output current (ma) 0 50 100 250 200 150 stable esr act8942-021 ldo output voltage noise ch1 ch1: v outx , 200v/div (ac coupled) time: 200ms/div act8942 rev 2, 15-nov-12 - 24 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers (t a = 25c, unless otherwise specified.) acin/chglev = 01 act8942-022 vsys voltage vs. vsys current 6.0 5.0 4.0 3.0 2.0 1.0 0 vsys voltage (v) vsys current (ma) 0 500 1000 1500 2000 2500 battery voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 battery voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 act8942-023 vsys voltage vs. chgin voltage vsys voltage (v) chgin voltage (v) 0 2 4 6 8 10 5.2 5.0 4.8 4.6 4.4 4.2 4.0 v vsys = 4.6v acin/chglev = 11 ch1: i vsys , 1.00a/div ch2: i bat , 1.00a/div ch3: v bat , 1.00v/div ch4: v vsys , 1v/div time: 200ms/div dccc and battery supplement modes act8942-027 ch3 ch4 ch1 ch2 v bat = 3.5v v vsys = 4.6v i vsys = 0-1.8a i charge = 1000ma v chgin = 5.1v-3a typical performance ch aracteristics cont?d act8942-024 charger current (ma) charger current vs. battery voltage 100 90 80 70 60 50 40 30 20 10 0 act8942-025 charger current (ma) charger current vs. battery voltage 500 450 400 350 300 250 200 150 100 50 0 v chgin = 5v acin = 0 chglev = 1 450ma usb v chgin = 5v acin = 0 chglev = 0 90ma usb act8942-026 charger current vs. battery voltage 1200 1000 800 600 400 200 0 battery voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 charger current (ma) r iset = 2.4k ? v chgin = 5v acin/chglev = 11 v bat falling v bat rising v bat falling v bat rising v bat falling v bat rising act8942 rev 2, 15-nov-12 - 25 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers (t a = 25c, unless otherwise specified.) typical performance ch aracteristics cont?d vac applied act8942-028 ch1 ch2 ch3 ch4 v chgin = 5v v bat = 3.5v r vsys = 100 ? acin/chglev = 01 ch1: i bat , 400ma/div ch2: v bat , 1v/div ch3: v vsys , 2v/div ch4: v chgin , 5v/div time: 40ms/div vac removed act8942-029 ch1 ch2 ch3 ch4 ch1: i bat , 200ma/div ch2: v vsys , 2v/div ch3: v bat , 1v/div ch4: v chgin , 5v/div time: 100ms/div v chgin = 5v v bat = 3.5v r vsys = 100 ? acin/chglev = 01 ch1: i bat , 1a/div ch2: v bat , 2v/div ch3: v vsys , 2v/div ch4: v chgin , 5v/div time: 40ms/div vac applied act8942-030 ch1 ch2 ch3 ch4 v chgin = 5v v bat = 3.97v r vsys = 47 ? acin/chglev = 11 vac removed act8942-031 ch4 ch3 ch2 ch1 ch1: i bat , 1a/div ch2: v vsys , 2v/div ch3: v bat , 2v/div ch4: v chgin , 5v/div time: 40ms/div v chgin = 5v v bat = 3.97v r vsys = 47 ? acin/chglev = 11 act8942 rev 2, 15-nov-12 - 26 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers system control information the act8942 is optimized for use in applications using the amlogic aml8726-m3 processor, supporting both the power domains as well as the signal interface for the processor. while the act8942 supports many possible configurations for powerin g these processors, one of the most common configurations is detailed in this datasheet. in general, this document refers to the act8942 pin names and functions. however, in cases where the description of interconnections between these devices benefits by doing so, both the act8942 pin names and the aml8726-m3 processor pin names are provided. when this is done, the aml8726-m3 pin names are located after the act8942 pin names, and are italicized and located inside parentheses. for example, pwren ( gpioao_2 ) refers to the logic signal applied to the act8942's pwren input, identifying that it is driven from the aml8726-m3?s gpioao_2 output. likewise, out1 (vcc1 .2v_ao) refers to act8942's out1 pin, identifying that it is connected to the aml8726-m3?s vcc1.2v_ao power domain. interfacing with the amlogic aml8726-m3 table 3: act8942 and amlogic aml8726-m3 power modes table 2: act8942 and amlogic aml8726-m3 power domains power domain act8942 channel type default voltage current capability vcc1.2v_ao reg1 dc/dc 1.25v/1.25v 1150ma vcc1.5v reg2 dc/dc 1.5v/1.5v 1150ma vddio reg3 dc/dc 3.0v/3.0v 1300ma vddio_ao reg4 ldo 3.0v 80ma avdd2.5v reg6 ldo 2.5v 320ma hdmi_vcc reg7 ldo 3.3v 320ma avdd3v reg5 ldo 3.0v 320ma power mode control state power domain state quiescent current normal pwrhld is assert ed, pwren is asserted. reg1, reg2, reg3, reg4, reg5, reg6 and reg7 are on. 420a sleep pwrhld is asserted, pwren is de-asserted. reg1, reg2 and reg4 are on, reg3, reg5, reg6 and reg7 are off. 250a system off pwrhld is de-asserted, pwren is de- asserted. reg1, reg2, reg3, reg4, reg5, reg6 and reg7 are off. <18a act8942 rev 2, 15-nov-12 - 27 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers control signals enable inputs the act8942 features a variety of control inputs, which are used to enable and disable outputs depending upon the desired mode of operation. pwren, pwrhld are logic inputs, while npbin is a unique, multi-function input. refer to table 5 for a description of which channels are controlled by each input. npbin multi-function input act8942 features the npbin multi-function pin, which combines system enable/disable control with a hardware reset function. select either of the two pin functions by asserting this pin, either through a direct connection to ga, or through a 50k ? resistor to ga, as shown in figure 2. manual reset function the second major function of the npbin input is to provide a manual-reset input for the processor. to manually-reset the processor, drive npbin directly to ga through a low impedance (less than 2.5k ? ). when this occurs, nrsto immediately asserts low, then remains asserted low until the npbin input is de-asserted and the reset time-out period expires. npbstat output npbstat is an open-drain output that reflects the state of the npbin input; npbstat is asserted low whenever npbin is asserted, and is high-z otherwise. this output is typically used as an interrupt signal to the processor, to initiate a software-programmable routine such as operating mode selection or to open a menu. connect npbstat to an appropriate supply voltage (typically out4) through a 10k ? or greater resistor. figure 2: npbin input system control information act8942 table 5: control pins pin name output npbin reg1, reg2, reg3, reg4, reg5, reg6, reg7 pwrhld reg1, reg2, reg4 pwren reg3, reg5, reg6, reg7 table 4: act8942 and amlogic aml8726-m3 signal interface act8942 direction amlogic aml8726-m3 pwren gpioao_2 scl gpioao_4 sda gpioao_5 vsel gpioao_3 nrsto resetn nirq gpioao_8 npbstat rtc_gpo pwrhld gpioao_6 act8942 rev 2, 15-nov-12 - 28 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers nrsto output nrsto is an open-drain output which asserts low upon startup or when manual reset is asserted via the npbin input. when asserted on startup, nrsto remains low until reset time-out period expires after out4 reaches its power-ok threshold. when asserted due to manual-reset, nrsto immediately asserts low, then remains asserted low until the npbin input is de-asserted and the reset time-out period expires. connect a 10k ? or greater pull-up resistor from nrsto to an appropriate voltage supply (typically out4). nirq output nirq is an open-drain out put that asserts low any time an interrupt is generated. connect a 10k ? or greater pull-up resistor from nirq to an appropriate voltage supply. nirq is typi cally used to drive the interrupt input of the system processor. many of the act8942's f unctions support interrupt- generation as a result of various conditions. these are typically masked by default, but may be unmasked via the i 2 c interface. for more information about the available fault conditions, refer to the appropriate sections of this datasheet. note that under some conditions a false interrupt may be generated upon initial startup. for this reason, it is recommended that the interrupt service routine check and validate n syslevmsk[ - ] and nfltmsk[ - ] bits before processing an interrupt generated by these bits. these interrupts may be validated by nsysstat[ - ], ok[ - ] bits. push-button control the act8942 is designed to initiate a system enable sequence when the npbin multi-function input is asserted. once this occurs, a power-on sequence commences, as described below. the power-on sequence must complete and the microprocessor must take control (by asserting pwren or pwrhld) before npbin is de-asserted. if the microprocessor is unable to complete its power-up routine successf ully before the user releases the push-button, the act8942 automatically shuts the syst em down. this provides protection against accidental or momentary assertions of the push-button. if desired, longer ?push-and-hold? times can be implemented by simply adding an additional time delay before control sequences the act8942 features a variety of control sequences that are optimiz ed for supporting system enable and disable, as well as sleep mode of amlogic aml8726-m3 application processor. enabling/disabling sequence a typical enable sequence is initiated whenever the following conditions occurs: 1) npbin is asserted low via 50k ? resistance, or 2) a valid input voltage is present at chgin . the enable sequence begins by enabling reg4. when reg4 reaches its power-ok threshold, nrsto is asserted low, resetting the microprocessor. reg1 is enabled after reg4 reaches its power-ok threshold for 2ms 2 , reg3 is enabled after reg4 reaches its power-ok threshold for 4ms 2 , reg2 is enabled after reg3 reaches its power-ok threshold for 2ms 2 , reg5, reg6 and reg7 are enabled after reg3 reaches its power-ok threshold for 4ms 2 . if reg4 is above its power-ok threshold when the reset timer expires, nrsto is de- asserted, allowing the microprocessor to begin its boot sequence. during the boot sequence, the microprocessor must assert pwrhld (gpioao_6), holding reg1, reg2 and reg4, and assert pwren (gpioao_2), holding reg3, reg5, reg6 and reg7 to ensure that the system remains powered after npbin is released. once the power-up routine is completed, the system remains enabled after the push-button is released as long as both pwrhld and pwren is asserted high. if the processor does not assert pwrhld before the user releases the push-button, the boot-up sequence is terminated and all regulators are disabled. th is provides protection against "false-enable", when the push-button is accidentally depressed, a nd also ensures that the system remains enabled only if the processor successfully completes the boot-up sequence. sleep mode sequence the act8942 supports amlogic aml8726-m3 processor?s sleep mode operation. once a successful power-up rout ine has been completed, sleep mode may be initiated through a variety of software-controlled mechanisms. sleep mode is typically initiated when the user presses the push-button during normal operation. pressing the push-button asserts the npbin input, which asserts the npbstat output, which interrupts the processor. in response to this interrupt the processor should de-assert pwren, disabling reg3, reg5, reg6 and reg7. pwrhld should remain asserted during sleep mode so that reg1, reg2 and reg4 remain enabled. : applicable only for act8942qj2##. : typical value shown, actual delay time may vary from (t-1ms ) x 88% to t x 112%, where t is the typical delay time setting. act8942 rev 2, 15-nov-12 - 29 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers standby voltage could be preset to lower voltages for sleep mode, the processor could assert vsel pin when entering sleep mode so that reg1 and reg2 outputs switch to lower voltages to reduce power consumption in sleep mode. waking up from sleep mode is typically initiated when the user presses the push-button again, which asserts npbstat. processors should respond by asserting pwren, which turns on reg3, reg5, reg6 and reg7, and de-assert vsel so that reg1 and reg2 go back to normal voltages, then normal operation may resume. disable sequence as with the enable sequence, a typical disable sequence is initiated when the user presses the push-button, which interrupts the processor via the npbstat output. the actual disable sequence is completely software-controlled, but typically involved initiating various ?clean-up? processes before finally de-assert pwren and pwrhld, disabling all regulators and shutting the system down. figure 3: enable/disable sequence : applicable only for act8942qj2##. act8942 rev 2, 15-nov-12 - 30 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers figure 4: sleep mode sequence : applicable only for act8942qj2##. act8942 rev 2, 15-nov-12 - 31 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers i 2 c interface the act8942 features an i 2 c interface that allows advanced programming capability to enhance overall system performance. to ensure compatibility with a wide range of system processors, the i 2 c interface supports clock speeds of up to 400khz (?fast-mode? operation) and uses standard i 2 c commands. i 2 c write-byte commands are used to program the act8942, and i 2 c read-byte commands are used to read the act8942?s internal registers. the act8942 always operates as a slave device, and is addressed using a 7-bit slave address followed by an eighth bit, which indicates whether the transaction is a read- operation or a write-operation, [1011011x]. sda is a bi-directional data line and scl is a clock input. the master device initiates a transaction by issuing a start condition, defined by sda transitioning from high to low while scl is high. data is transferred in 8-bit packets, beginning with the msb, and is clocked-in on the rising edge of scl. each packet of data is followed by an ?acknowledge? (ack) bit, used to confirm that the data was transmitted successfully. for more information regarding the i 2 c 2-wire serial interface, go to the nxp website: http://www.nx p.com. voltage monitor and interrupt programmable system voltage monitor the act8942 features a programmable system- voltage monitor, which monitors the voltage at vsys and compares it to a programmable threshold voltage. the programmable voltage threshold is programmed by syslev[3:0], as shown in table 6. syslev[ ] is set to 3.0v by default. there is a 200mv rising hysteresis on syslev[ ] threshold such that v vsys needs to be 3.2v(typ) or higher in order to power up the ic. the nsysstat[ - ] bit reflects the output of an internal voltage comparator that monitors v vsys relative to the syslev[ - ] voltage threshold, the value of nsystat[ - ] = 1 when v vsys is lower than the syslev[ - ] voltage threshold, and nsystat[ - ] = 0 when v vsys is higher than the syslev[ - ] voltage threshold. note that the syslev[ - ] voltage threshold is defined for falling voltages, and that the comparator produces about 200mv of hysteresis at vsys. as a result, once v vsys falls below the syslev threshold, its voltage must increase by more than about 200mv to clear that condition. after the ic is powered up, the act8942 responds in one of two ways when the voltage at vsys falls below the syslev[ - ] voltage threshold: 1) if nsysmode[ - ] = 1 (default case), when system v o l t a g e l e v e l i n t e r r u p t i s u n m a s k e d (nsyslevmsk[ ]=1) and v vsys falls below the programmable threshold, the act8942 asserts nirq, providing a software ?under-voltage alarm?. the response to this interrupt is controlled by the cpu, but will typically initiate a controlled shutdown sequence either or alert the user that the battery is low. in this case the interrupt is cleared when v vsys rises up again above the syslev rising threshold and nsysstat[ - ] is read via i 2 c. 2) if nsysmode[ - ] = 0, when v vsys falls below the programmable threshold the act8942 shuts down, immediately disabling all regulators. this option is useful for implementing a programmable ?under- voltage lockout? function that forces the system off when the battery voltage falls below the syslev threshold voltage. since this option does not support a controlled shutdown sequence, it is generally used as a "fail-safe" to shut the system down when the battery voltage is too low. table 6: syslev falling threshold precision voltage detector the lbi input connects to one input of a precision voltage comparator, which can be used to monitor a system voltage such as the battery voltage. an external resistive-divider network can be used to set voltage monitoring thresholds, as shown in functional block diagram . the output of the comparator is present at the nlbo open-drain output. syslev[3:0] syslev falling threshold (hysteresis = 200mv) 0000 2.3 0001 2.4 0010 2.5 0011 2.6 0100 2.7 0101 2.8 0110 2.9 0111 3.0 1000 3.1 1001 3.2 1010 3.3 1011 3.4 1100 3.5 1101 3.6 1110 3.7 1111 3.8 functional description act8942 rev 2, 15-nov-12 - 32 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers thermal shutdown the act8942 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. this circuitry disables all regulators if the act8942 die temperature exceeds 160c, and prevents the regulators from being enabled until the ic temperature drops by 20c (typ). act8942 rev 2, 15-nov-12 - 33 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers general description the act8942 features three synchronous, fixed- frequency, current-mode pwm step down converters that achieve peak efficiencies of up to 97%. reg1 and reg2 are capable of supplying up to 1150ma of output current, while reg3 supports up to 1300ma. these regulators operate with a fixed frequency of 2mhz, minimizing noise in sensitive applications and allowing the use of small external components. 100% duty cycle operation each regulator is capable of operating at up to 100% duty cycle. duri ng 100% duty-cycle operation, the high-side power mosfet is held on continuously, providing a direct connection from the input to the output (throug h the inductor), ensuring the lowest possible dropout voltage in battery powered applications. synchronous rectification reg1, reg2, and reg3 each feature integrated n- channel synchronous rectifiers, maximizing efficiency and minimizing the total solution size and cost by eliminating the nee d for external rectifiers. soft-start when enabled, each output voltages tracks an internal 400 s soft-start ramp, minimizing input current during startup and allowing each regulator to power up in a smooth, monotonic manner that is independent of output load conditions. compensation each buck regulator utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. no compensation design is required; simply follow a few simple guidelines described below when choosing external components. input capacitor selection the input capacitor reduces peak currents and noise induced upon the voltage source. a 4.7 f ceramic capacitor is recommended for each regulator in most applications. output capacitor selection for most applications, 22 f ceramic output capacitors are recommended for reg1, reg2 and reg3. despite the advantages of ceramic capacitors, care must be taken during the design process to ensure stable operation over the full operating voltage and temperature range. ceramic capacitors are available in a variety of dielectrics, each of which exhibits different characteristics that can greatly affect performance over their temperature and voltage ranges. two of the most common dielectrics are y5v and x5r. whereas y5v dielectrics are inexpensive and can provide high capacit ance in small packages, their capacitance varies greatly over their voltage and temperature ranges and are not recommended for dc/dc applications. x5r and x7r dielectrics are more suitable for output capacitor applications, as their characteristics ar e more stable over their operating ranges, and are highly recommended. inductor selection reg1, reg2, and reg3 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. these devices were optimized for operation with 2.2 h inductors, although i nductors in the 1.5 h to 3.3 h range can be used. choose an inductor with a low dc-resistance, and avoid inductor saturation by choosing inductors with dc ratings that exceed the maximum output current by at least 30%. configuration options output voltage programming by default, each regulator powers up and regulates to its default output voltage. output voltage is selectable by setting vsel pin that when vsel is low, output voltage is programmed by vset1[ - ] bits, and when vsel is high, output voltage is programmed by vset2[ - ] bits. however, once the system is enabled, each regulator's output voltage may be independently programmed to a different value, typically in order to minimize the power consumption of the microprocessor during some operating modes. program the output voltages via the i 2 c serial interface by writing to the regulator's vset1[ - ] register if vsel is low or vset2[ - ] register if vsel is high as shown in table 7. enable / disable control during normal operation, each buck may be enabled or disabled via the i 2 c interface by writing to that regulator's on[ ] bit. the regulator accept rising or falling edge of on[ ] bit as on/off signal. to enable the regulator, clear on[ ] to 0 first then set to step-down dc/dc regulators act8942 rev 2, 15-nov-12 - 34 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers 1. to disable the regulator, set on[ ] to 1 first then clear it to 0. reg1, reg2, reg3 turn-on delay each of reg1, reg2 and reg3 features a programmable turn-on delay which help ensure a reliable qualification. this delay is programmed by delay[2:0], as shown in table 8. table 8: regx/delay[ ] turn-on delay operating mode by default, reg1, reg2, and reg3 each operate in fixed-frequency pwm mode at medium to heavy loads, while automatically transitioning to a proprietary power-saving mode at light loads in order to maximize standby battery life. in applications where low noise is critical, force fixed- frequency pwm operation across the entire load current range, at the expense of light-load efficiency, by setting the mode[ ] bit to 1. ok[ ] and output fault interrupt each dc/dc features a power-ok status bit that can be read by the system microprocessor via the i 2 c interface. if an output voltage is lower than the power-ok threshold, typically 7% below the programmed regulation voltage, that regulator's ok[ ] bit will be 0. if a dc/dc's nfltmsk[ - ] bit is set to 1, the act8942 will interrupt the pr ocessor if that dc/dc's output voltage falls below the power-ok threshold. in this case, nirq will assert low and remain asserted until either the regulator is turned off or back in regulation, and the ok[ ] bit has been read via i 2 c. pcb layout considerations high switching frequencies and large peak currents make pc board layout an important part of step- down dc/dc converter design. a good design minimizes excessive emi on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. step-down dc/dcs exhibi t discontinuous input current, so the input capacitors should be placed as close as possible to the ic, and avoiding the use of via if possible. the inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. the ground nodes for each regulator's power loop should be connected at a single point in a star-ground configuration, and this point should be connected to the backside ground plane with multiple via. the output node for each regulator should be connected to its corresponding outx pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. finally, the exposed pad should be directly connected to the backside ground plane using multiple via to achieve low electrical and thermal resistance. regx/vset[2:0] 000 001 010 011 100 101 110 111 000 0.600 0.800 1.000 1.200 1.600 2.000 2.400 3.200 001 0.625 0.825 1.025 1.250 1.650 2.050 2.500 3.300 010 0.650 0.850 1.050 1.300 1.700 2.100 2.600 3.400 011 0.675 0.875 1.075 1.350 1.750 2.150 2.700 3.500 100 0.700 0.900 1.100 1.400 1.800 2.200 2.800 3.600 101 0.725 0.925 1.125 1.450 1.850 2.250 2.900 3.700 110 0.750 0.950 1.150 1.500 1.900 2.300 3.000 3.800 111 0.775 0.975 1.175 1.550 1.950 2.350 3.100 3.900 regx/vset[5:3] table 7: regx/vset[ ] output voltage setting delay[2] delay[1] delay[0] turn-on delay 0 0 0 0 ms 0 0 1 2 ms 0 1 0 4 ms 0 1 1 8 ms 1 0 0 16 ms 1 0 1 32 ms 1 1 0 64 ms 1 1 1 128 ms act8942 rev 2, 15-nov-12 - 35 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers general description reg4, reg5, reg6, and reg7 are low-noise, low-dropout linear regulators (ldos) that supply up to 80ma, 320ma, 320ma and 320ma, respectively. each ldo has been optimized to achieve low noise and high-psrr, achieving more than 65db psrr at frequencies up to 10khz. output current limit each ldo contains current-limit circuitry featuring a current-limit fold-back function. during normal and moderate overload conditions, the regulators can support more than their rated output currents. during extreme overload conditions, however, the current limit is reduced by approximately 30%, reducing power dissipation within the ic. compensation the ldos are internally compensated and require very little design effort, simply select input and output capacitors according to the guidelines below. input capacitor selection each ldo requires a small ceramic input capacitor to supply current to suppo rt fast transients at the input of the ldo. bypassing each inl pin to ga with 1 f. high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. output capacitor selection reg4 requires a 1.5uf ceramic output capacitor and reg5, reg6 and reg7 require a 3.3 f ceramic output capacitor for stability. for best performance, each output capacitor should be connected directly between the output and ga pins, as close to the output as possible, and with a short, direct connection. high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. configuration options output voltage programming by default, each ldo powers up and regulates to its default output voltage. once the system is enabled, each output voltage may be independently programmed to a different value by writing to the regulator's vset[ - ] register via the i 2 c serial interface as shown in table 5. enable / disable control during normal operation, each ldo may be enabled or disabled via the i 2 c interface by writing to that ldo's on[ ] bit. the regulator accept rising or falling edge of on[ ] bit as on/off signal. to enable the regulator, clear on[ ] to 0 first then set to 1. to disable the regulator, set on[ ] to 1 first then clear it to 0. reg4, reg5, reg6, reg7 turn-on delay each of reg4, reg5, reg6 and reg7 features a programmable turn-on delay which help ensure a reliable qualification. this delay is programmed by delay[2:0], as shown in table 4. output discharge each of the act8942?s ldos features an optional output discharge function, which discharges the output to ground through a 1.5k ? resistance when the ldo is disabled. this feature may be enabled or disabled by setting dis[ - ]; set dis[ - ] to 1 to enable this function, clear dis[ - ] to 0 to disable it. low-power mode each of act8942's ldos features a lowiq[ - ] bit which, when set to 1, reduces the ldo's quiescent current by about 16%, saving power and extending battery lifetime. ok[ ] and output fault interrupt each ldo features a power-ok status bit that can be read by the system mi croprocessor via the interface. if an output voltage is lower than the power-ok threshold, typically 11% below the programmed regulation voltage, the value of that regulator's ok[ - ] bit will be 0. if a ldo's nfltmsk[ - ] bit is set to 1, the act8942 will interrupt the processor if that ldo's output voltage falls below the power-ok threshold. in this case, nirq will assert low and remain asserted until either the regulator is turned off or back in regulation, and the ok[ - ] bit has been read via i 2 c. pcb layout considerations the act8942?s ldos provide good dc, ac, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. when designing a pcb, however, careful layout is necessary to prevent other circuitry from degrading ldo performance. a good design places input and output capacitors as close to the ldo inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. output traces should be routed to avoid low-noise, low-dropou t linear regulators act8942 rev 2, 15-nov-12 - 36 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers close proximity to noisy nodes, particularly the sw nodes of the dc/dcs. refbp is a noise-filtered reference, and internally has a direct connection to the linear regulator controller. any noise injected into refbp will directly affect the outputs of the linear regulators, and therefore special care should be taken to ensure that no noise is injected to the outputs via refbp. as with the ld o output capacitors, the refbp bypass capacitor should be placed as close to the ic as possible, with short, direct connections to the star-ground. avoid the use of via whenever possible. noisy nodes, such as from the dc/dcs, should be routed as far away from refbp as possible. act8942 rev 2, 15-nov-12 - 37 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers general description the act8942 features an advanced battery charger that incorporates the patent-pending activepath architecture for system power selection . this combination of circuits provides a complete, advanced battery-managem ent system that automatically selects the best available input supply, manages charge current to ensure system power availability, and provides a complete, high- accuracy (0.5%), thermall y regulated, full-featured single-cell linear li+ charger that can withstand input voltages of up to 12v. activepath architecture the activepath architecture performs three important functions: 1) system configuration optimization 2) input protection 3) battery-management system configuration optimization the activepath circuitry monitors the state of the input supply, the battery, and the system, and automatically reconfigures itself to optimize the power system. if a valid input supply is present, activepath powers the system from the input while charging the battery in parallel. this allows the battery to charge as quickly as possible, while supplying the system. if a valid input supply is not present, activepath powers the system from the battery. finally, if the input is present and the system current requireme nt exceeds the capability of the input supply, activepath allows system power to be drawn from both the battery and the input supply. input protection input over-voltage protection the activepath circuitry features input over-voltage protection circuitry. this circuitry disables charging when the input voltage exceeds the voltage set by ovpset[ - ] as shown in table 9, but stands off the input voltage in order to protect the system. note that the adjustable ovp threshold is intended to provide the charge cycle with adjustable immunity against upward voltage transients on the input, and is not intended to allow continuous charging with input voltages above the c harger's normal operating voltage range. independent of the ovpset[ - ] setting, the charge cycle is not allowed to resume until the input voltage falls back into the charger's normal operating voltage range (i.e. below 6.0v). in an input over-voltage condition this circuit limits v vsys to 4.6v, protecting any circuitry connected to vsys from the over-voltage condition, which may exceed this circuitry's volt age capability. this circuit is capable of withstanding input voltages of up to 12v. table 9: input over-voltage protection setting input supply overload protection the activepath circuitry monitors and limits the total current drawn from the input supply to a value set by the acin and chglev inputs, as well as the resistor connected to iset. drive acin to a logic- low for ?usb mode?, which limits the input current to either 100ma, when chglev is driven to a logic- low, or 450ma, when chglev is driven to a logic- high. drive acin to a logic-high for ?ac-mode?, which limits the input current to 2a, typically. input under voltage lockout if the input voltage applied to chgin falls below 3.5v (typ), an input un der-voltage condition is detected and the charger is disabled. once an input under-voltage condition is detected, a new charge cycle will initiate when t he input exceeds the under- voltage threshold by at least 500mv. battery management the act8942 features a full-featured, intelligent charger for lithium-based cells, and was designed specifically to provide a complete charging solution with minimum system design effort. the core of the charger is a cc/cv (constant- current/constant-voltage), linear-mode charge controller. this controller incorporates current and voltage sense circuitry, an internal 70m ? power mosfet, thermal-regulation circuitry, a full- featured state machine that implements charge control and safety features, and circuitry that eliminates the reverse blocking diode required by conventional charger designs. the charge termination voltage is highly accurate (0.5%), and features a selection of charge safety time-out periods that pr otect the system from operation with damaged cells. other features activepath tm charger ovpset[1] ovpset[0] ovp threshold 0 0 6.6v 0 1 7.0v 1 0 7.5v 1 1 8.0v act8942 rev 2, 15-nov-12 - 38 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers include pin-programmable fast-charge current and one current-limited nstat out put that can directly drive led indicator or provide a logic-level status signal to the host microprocessor . dynamic charge current control (dccc) the act8942's activepath charger features dynamic charge current cont rol (dccc) circuitry, which acts to ensure that the system remains powered while operating within the maximum output capability of the power ada pter. the dccc circuitry continuously monitors v vsys , and if the voltage at vsys drops by more than 200mv, the dccc circuitry automatically reduces charge current in order to prevent v vsys from continuing to drop. charge current programming the act8942's activepath charger features a flexible charge current-programming scheme that combines the convenience of internal charge current programming with the flexibility of resistor based charge current programming. current limits and charge current programming are managed as a function of the acin and chglev pins, in combination with r iset , the resistance connected to the iset pin. acin is a logic input that configures the current-limit of activepath 's linear regulator as well as that of the battery charger. acin feat ures a precise 1.2v logic threshold, so that the input voltage detection threshold may be adjusted with a simple resistive voltage divider. this input also allows a simple, low- cost dual-input charger switch to be implemented with just a few, low-cost components. when the voltage at acin is above the 1.2v threshold, the charger operates in ?ac-mode? with a charge current programmed by r iset , and the r iset is given by: r iset (k ? ) = 2336 (1v/i chg (ma)) - 0.205 with a given r iset then charge current will reduce 5 times when chglev is driven low. when acin is below the 1.2v threshold, the charger operates in ?usb-mode?, with a maximum chgin input current and c harge current defined by the chglev input; 450ma, if chglev is driven to a logic-high, or 100ma, if chglev is driven to a logic-low. the act8942's charge current settings are summarized in table 10. note that the actual charge current may be limited to a current lower than the programmed fast charge current due to the act8942?s internal thermal regulation loop. see the thermal regulation section for more information. charger input interrupts in order to ease input supply detection and eliminate the size and cost of external detection circuitry, the charger has the ability to generate interrupts based upon the stat us of the input supply. this function is capable of generating an interrupt when the input is connected, disconnected, or both. an interrupt is generated any time the input supply is connected when instat[ ] bit is set to 1 and the incon[ - ] bit is set to 1, and an interrupt is generated any time the input supply is disconnected when instat[ ] bit is set to 1 and the indis[ ] bit is set to 1. indat[ - ] indicates the status of the chgin input supply. a value of 1 indicates that a valid chgin input (chgin uvlo threshold act8942 rev 2, 15-nov-12 - 40 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers charge-control state machine precondition state a new charging cycle begins with the precondition state, and operation continues in this state until v bat exceeds the precondition threshold voltage. when operating in precondition state, t he cell is charged at 10% of the programmed maximum fast-charge constant current, i chg . once v bat reaches the precondition threshold voltage, the state machine jumps to the fast- charge state. if v bat does not reach the precondition threshold voltage before the precondition time-out peri od expires, then the state machine jumps to the time-out-fault state in order to prevent charging a damaged cell. see the charge safety timers section for more information. fast-charge state in the fast-charge state, the charger operates in constant-current (cc) mode and regulates the charge current to the current set by r iset . charging continues in cc mode until v bat reaches the charge termination voltage (v term ), at which point the state- machine jumps to the top-off state. if v bat does not reach v term before the total time out period expires then the state-machine will jump to the ?eoc? state and will re-initi ate a new charge cycle after 32ms ?relax?. see the current limits and charge current programming sections for more information about setting the maximum charge current. top-off state in the top-off state, the cell charges in constant- voltage (cv) mode. in cv mode operation, the charger regulates its output voltage to the 4.20v charge termination voltage, and the charge current is naturally reduced as the cell approaches full charge. charging continue s until the charge current drops to end-of-charge current threshold, at which point the state machine jumps to the end- of-charge (eoc) state. if the state-machine does not jump out of the top- off state before the total-charge time-out period expires, then the state machine jumps to the eoc state and will re-initiate a new charge cycle if v bat falls below termination voltage 205mv (typ). for more information about the charge safety timers, see the charging safety times section. end-of-charge (eoc) state in the end-of-charge (e oc) state, the charger presents a high-impedance to the battery, minimizing battery current drain and allowing the cell to ?relax?. the charger continues to monitor the cell voltage, and re-initiates a charging sequence if the cell voltage drops to 205mv (typ) below the charge termination voltage. suspend state the state-machine jumps to the suspend state any time the battery is removed, and any time the input voltage either falls below the chgin uvlo threshold or exceeds the ovp threshold. once none of these conditions are present, a new charge cycle initiates. a charging cycle may also be suspended manually by setting the suspend[ ] bit. in this case, initiate a new charging sequence by clearing suspend[ ] to 0. state machine interrupts the charger features the ability to generate interrupts when the charger state machine transitions, based upon the status of the chg_ bits. set chgeocin[ ] bit to 1 and chgstat[ ] bit to 1 to generate an interrupt when the charger state machine goes into the end-of-charge (eoc) state. set chgeocout[ ] bit to 1 and chgstat[ ] bit to 1 to generate an interrupt when the charger state machine exits the eoc state. chgdat[ ] indicates the status of the charger state machine. a value of 1 indicates that the charger state machine is in end-of-charge state, a value of 0 indicates the charger state machine is in other states. when an interrupt is generat ed by the charger state machine, reading the chgstat[ ] returns a value of 1. chgstat[ ] is automatically cleared to 0 upon reading. when no interrupt is generated by the charger state machine, reading the chgstat[ ] returns a value of 0. for additional information about the charge cycle, cstate[1:0] may be read at any time via i 2 c to determine the current charging state. table 11: charging status indication cstate[1] cstate[0] state machine status 1 1 precondition state 1 0 fast-charge/ top-off state 0 1 end-of-charge state 0 0 suspend/disabled/ fault state act8942 rev 2, 15-nov-12 - 41 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers tottimo[1] tottimo[0] total time-out period 0 0 3 hrs 0 1 4 hrs 1 0 5 hrs 1 1 disabled thermal regulation the charger features an internal thermal regulation loop that monitors die temperature and reduces charging current as needed to ensure that the die temperature does not exceed the thermal regulation threshold of 110c. this feature protects against excessive junction temperature and makes the device more accommodating to aggressive thermal designs. note, however, that attention to good thermal designs is required to achieve the fastest possible charge time by maximizing charge current. charge safety timers the charger features programmable charge safety timers which help ensure a safe charge by detecting potentially damaged cells. these timers are programmable via the pretimo[1:0] and tottimo[1:0] bits, as shown in table 12 and table 13. note that in order to account for reduced charge current resulting from dccc operation in thermal regulation mode, the charge time-out periods are extended proportionally to the reduction in charge current. as a result, the actual safety period may exceed the nominal timer period. charger timer interrupts the charger features the ability to generate interrupts based upon the status of the charge timers. set the timrpre[ ] bit to 1 and timrstat[ ] bit to 1 to generate an interrupt when the precondition timer expires. set the timrtot[ ] bit to 1 and timrstat[ ] bit to 1 to generate an interrupt when the total- charge timer expires. timrdat[ ] indicates the status of the charge timers. a value of 1 indicates a precondition time- out or a total charge time-out occurs, a value of 0 indicates other cases. when an interrupt is generated by the charge timers, reading the timrstat[ ] returns a value of 1. timrstat[ ] is automatically cleared to 0 upon reading. when no interrupt is generated by the charge timers, reading the timrstat[ ] returns a value of 0. table 12: precondition safety timer setting table 13: total safety timer setting charge status indicator the charger provides a charge-status indicator output, nstat. nstat is an open-drain output which sinks current when the charger is in an active-charging state, and is high-z otherwise. nstat features an internal 8ma current limit, and is capable of directly driving a led without the need of a current-limiting resi stor or other external circuitry. to drive an led, simply connect the led between nstat pin and an appropriate supply, such as vsys. for a logic-level charge status indication, simply connect a resistor from nstat to an appropriate voltage supply. table 14: charging status indication reverse-current protection the charger includes internal reverse-current protection circuitry that eliminates the need for blocking diodes, reducing solution size and cost as well as dropout voltage relative to conventional battery chargers. when the voltage at chgin falls below v bat , the charger automatically reconfigures its power switch to minimize current drawn from the battery. battery temperature monitoring in a typical application, the th pin is connected to the battery pack's thermistor input, as shown in figure 7. the charger continuously monitors the temperature of the battery pack by injecting a pretimo[1] pretimo[0] precondition time-out period 0 0 40 mins 0 1 60 mins 1 0 80 mins 1 1 disabled state nstat precondition active fast-charge active top-off active end-of-charge high-z suspend high-z temperature fault high-z time-out-fault high-z act8942 rev 2, 15-nov-12 - 42 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers 102 a (typ) current into the thermistor (via the th pin) and sensing the voltage at th. the voltage at th is continuously monitored, and charging is suspended if the voltage at th exceeds either of the internal v thh and v thl thresholds of 0.5v and 2.51v, respectively. the net resistance (from th to ga) required to cross the thresholds are given by: 102 a rnom khot = 0.5v rnom khot 5k ? 102 a rnom kcold = 2.51v rnom kcold 25k ? where rnom is the nominal thermistor resistance at room temperature, and khot and kcold represent the ratios of the thermistor's resistance at the desired hot and cold thresholds, respectively, to the resistance at 25c. battery temperature interrupts in order to ease detecting the status of the battery temperature, the charger features the ability to generate interrupts based upon the status of the battery temperature. set the tempout[ ] bit to 1 and tempstat[ ] bit to 1 to generate an interrupt when battery temperature goes out of the valid temperature range. set the tempin[ ] bit to 1 and tempstat[ ] bit to 1 to generate an interrupt when battery temperature returns to the valid range. tempdat[ ] indicates the status of the battery temperature. a value of 1 indicates the battery temperature is inside of the valid range, a value of 0 indicates the battery is outside of the valid range. when an interrupt is generated by the battery temperature event, reading the tempstat[ ] returns a value of 1. tempstat[ ] is automatically cleared to 0 upon reading. when no interrupt is generated by the battery temperature event, reading the tempstat[ ] returns a value of 0. figure 7: simple configuration act8942 act8942 rev 2, 15-nov-12 - 43 - www.active-semi.com activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. copyright ? 2012 active-semi, inc. innovative power tm active-semi proprietary D for authorized recipients and customers tqfn55-40 package outline and dimensions symbol dimension in millimeters dimension in inches min max min max a 0.700 0.800 0.028 0.031 a1 0.200 ref 0.008 ref a2 0.000 0.050 0.000 0.002 b 0.150 0.250 0.006 0.010 d 4.900 5.100 0.193 0.201 e 4.900 5.100 0.193 0.201 d2 3.450 3.750 0.136 0.148 e2 3.450 3.750 0.136 0.148 e 0.400 bsc 0.016 bsc l 0.300 0.500 0.012 0.020 r 0.300 0.012 active-semi, inc. reserves the right to modify the circuitry or specifications without notice. user s should evaluate each product to make sure that it is suitable for their applicat ions. active-semi products are not intended or authorized for use as critical components in life-support dev ices or systems. active-semi, inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. active-semi and its logo are trademarks of active-semi, inc. for more information on this and other products, contact sales@active-semi.com or visit http://www.active-semi.com . is a registered trademark of active-semi. mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: active-semi: ? act8942qj133-t |
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